\n\t\uff082\uff09 \u6700\u9ad8\u5de5\u4f5c\u901f\u73872Mbps\uff0c\u9ad8\u6548GFSK\u8c03\u5236\uff0c\u6297\u5e72\u6270\u80fd\u529b\u5f3a\uff0c\u7279\u522b\u9002\u5408\u5de5\u4e1a\u63a7\u5236\u573a\u5408<\/p>\n
\n\t\uff083\uff09 126 \u9891\u9053\uff0c\u6ee1\u8db3\u591a\u70b9\u901a\u4fe1\u548c\u8df3\u9891\u901a\u4fe1\u9700\u8981<\/p>\n
\n\t\uff084\uff09 \u5185\u7f6e\u786c\u4ef6CRC \u68c0\u9519\u548c\u70b9\u5bf9\u591a\u70b9\u901a\u4fe1\u5730\u5740\u63a7\u5236<\/p>\n
\n\t\uff085\uff09 \u4f4e\u529f\u80171.9 - 3.6V \u5de5\u4f5c\uff0c\u5f85\u673a\u6a21\u5f0f\u4e0b\u72b6\u6001\u4e3a22uA\uff1b\u6389\u7535\u6a21\u5f0f\u4e0b\u4e3a900nA<\/p>\n
\n\t\uff086\uff09 \u5185\u7f6e2.4Ghz \u5929\u7ebf\uff0c\u4f53\u79ef\u5c0f\u5de715mm X29mm<\/p>\n
\n\t\uff087\uff09 \u6a21\u5757\u53ef\u8f6f\u4ef6\u8bbe\u5730\u5740\uff0c\u53ea\u6709\u6536\u5230\u672c\u673a\u5730\u5740\u65f6\u624d\u4f1a\u8f93\u51fa\u6570\u636e\uff08\u63d0\u4f9b\u4e2d\u65ad\u6307\u793a\uff09\uff0c\u53ef\u76f4\u63a5\u63a5\u5404\u79cd\u5355\u7247\u673a<\/u>\u4f7f\u7528\uff0c\u8f6f\u4ef6\u7f16\u7a0b\u975e\u5e38\u65b9\u4fbf<\/p>\n
\n\t![\"nRF24L01\u65e0\u7ebf\u6a21\u5757\u5728PIC16F877\u5355\u7247\u673a\u4e0a\u7684\u5e94\u7528\u89e3\u6790\"](\"http:\/\/www.szryc.com\/uploads\/allimg\/191126\/1605014514-0.png\")
<\/p>\n
\n\t![\"nRF24L01\u65e0\u7ebf\u6a21\u5757\u5728PIC16F877\u5355\u7247\u673a\u4e0a\u7684\u5e94\u7528\u89e3\u6790\"](\"http:\/\/www.szryc.com\/uploads\/allimg\/191126\/1605012362-1.jpg\")
<\/p>\n
\n\t\u901a\u8fc7SPI<\/u>\u65b9\u5f0f\u5b8c\u6210\u6570\u636e\u7684\u4ea4\u6362\uff0c\u5305\u62ec\u6570\u636e\u7684\u53d1\u9001\uff0c\u6570\u636e\u7684\u63a5\u6536\u3002\u8bf4\u660e\u4e00\u4e0b\uff0c\u5355\u7247\u673a\u4e2d\u5982\u679c\u6ca1\u6709SPI\u7684\u786c\u4ef6\u7535\u8def<\/u>\uff0c\u6211\u4eec\u53ef\u4ee5\u4f7f\u7528\u5355\u7247\u673a\u7684\u666e\u901aIO\u53e3\u8fdb\u884cSPI\u7684\u65f6\u5e8f\u6a21\u62df\uff0c\u53ea\u8981\u7b26\u5408\u65e0\u7ebf\u6a21\u5757\u7684\u65f6\u5e8f\u903b\u8f91\uff0c\u4e00\u6837\u80fd\u63a7\u5236\u65e0\u7ebf\u6a21\u5757\u7684\u901a\u4fe1\u3002FPGA<\/u>\u662f\u53ef\u7f16\u7a0b\u903b\u8f91\uff0c\u6700\u5927\u7684\u7279\u70b9\u5c31\u662f\u7075\u6d3b\uff0c\u7528\u6237\u53ef\u6839\u636e\u9700\u6c42\u52a0\u5165\u6240\u9700\u8981\u7684\u903b\u8f91\u5668\u4ef6<\/u>\uff0c\u5f53\u7136\u5b83\u6240\u5305\u542b\u7684\u903b\u8f91\u5355\u5143\u4e5f\u662f\u76f8\u5f53\u7684\u4e30\u5bcc\uff0c\u6709SPI\u786c\u4ef6\u6a21\u5757\u3002\u8fd9\u6837\u7528\u6237\u5c31\u7701\u53bb\u4e86SPI\u65b9\u5f0f\u7684\u65f6\u5e8f\u903b\u8f91\uff0c\u53ef\u4ee5\u66f4\u597d\u7684\u4e13\u6ce8\u4e8e\u529f\u80fd\u7684\u5f00\u53d1\u3002<\/p>\n
\n\t\u5355\u7247\u673a\uff1a\u8fd9\u91cc\u6211\u4eec\u4f7f\u7528\u7684\u5355\u7247\u673a\u578b\u53f7\u4e3aPIC16F877\u3002<\/p>\n
\n\t![\"nRF24L01\u65e0\u7ebf\u6a21\u5757\u5728PIC16F877\u5355\u7247\u673a\u4e0a\u7684\u5e94\u7528\u89e3\u6790\"](\"http:\/\/www.szryc.com\/uploads\/allimg\/191126\/16050143D-2.jpg\")
<\/p>\n
\n\t\u56fe1.3 NRF24L01\u63a5\u5165PIC\u7684\u539f\u7406\u56fe<\/p>\n
\n\t\u8bf4\u660e\uff1a\u4ece\u56fe1.3\u4e2d\u53ef\u4ee5\u770b\u51fa\uff0c\u4e3b\u8981\u662f\u56fe1.1\u4e2d\u76846\u4e2a\u4fe1\u53f7\uff08\u8fd8\u67092\u4e2a\u662f\u5730\u4e0e\u7535\u6e90\uff09\u63a5\u5165\u5355\u7247\u673a\u4e2d\u3002\u800c\u90a3\u4e9b\u5f15\u811a\u662f\u666e\u901a\u7684IO\u53e3\uff0c\u9700\u8981\u7528\u6237\u6a21\u4effSPI\u65f6\u5e8f\u8fdb\u884c\u63a7\u5236\u3002<\/p>\n
\n\t\u65e0\u7ebf\u6a21\u5757\u8fdb\u884c\u6570\u636e\u7684\u4ea4\u6362\u5c31\u662f\u6570\u636e\u7684\u53d1\u9001\u4e0e\u6570\u636e\u7684\u63a5\u6536\uff0c\u4e0b\u9762\u5c06\u4ece\u8fd92\u4e2a\u65b9\u9762\u8fdb\u884c\u4ecb\u7ecd\u3002\u4e0d\u7ba1\u662f\u6570\u636e\u7684\u53d1\u9001\u8fd8\u662f\u6570\u636e\u7684\u63a5\u6536\uff0c\u8981\u60f3\u63a7\u5236\u597dNRF24L01\u65e0\u7ebf\u6a21\u5757\uff0c\u5148\u8981\u901a\u8fc7SPI\u65b9\u5f0f\u5bf9\u65e0\u7ebf\u6a21\u5757\u8fdb\u884c\u914d\u7f6e\uff0c\u53ea\u9700\u8981\u5f80\u5b83\u5bf9\u5e94\u7684\u5bc4\u5b58\u5668<\/u>\u91cc\u5199\u5165\u6570\u503c\u4fbf\u53ef\u3002<\/p>\n
\n\t\u5148\u5b9a\u4e49\u4e00\u4e0bPIC\u4e0a\u7684\u5b8f\uff0c\u4e0b\u9762\u6211\u4eec\u5c31\u53ef\u4ee5\u5f88\u65b9\u4fbf\u7684\u5bf9PIC\u7684\u5f15\u811a\u8fdb\u884c\u64cd\u4f5c\u3002<\/p>\n
\n\t1 #define MI<\/u>SO RC2<\/p>\n
\n\t2 #define MOSI RC3<\/p>\n
\n\t3 #define SCK RD0<\/p>\n
\n\t4 #define CE RD2<\/p>\n
\n\t5 #define CSN RD1<\/p>\n
\n\t6 #define IRQ RC1<\/p>\n
\n\t7 #define LED<\/u> RD3<\/p>\n
\n\t8 #define KEY0 RB0<\/p>\n
\n\t9 #define KEY1 RB1<\/p>\n
\n\t10 #define KEY2 RB2<\/p>\n
\n\t11 #define KEY3 RB3<\/p>\n
\n\t12 #define KEY4 RB4<\/p>\n
\n\t13 #define KEY5 RB5<\/p>\n
\n\t14 #define KEY6 RB6<\/p>\n
\n\t15 #define KEY7 RB7<\/p>\n
\n\tNRF24L01\u65e0\u7ebf\u6a21\u5757\u7684\u5bc4\u5b58\u5668<\/p>\n
\n\t1 \/\/*******************NRF24L01\u5bc4\u5b58\u5668\u6307\u4ee4<\/p>\n
\n\t2 #define READ_REG 0x00 \/\/ \u8bfb\u5bc4\u5b58\u5668\u6307\u4ee4<\/p>\n
\n\t3 #define WRITE<\/u>_REG 0x20 \/\/ \u5199\u5bc4\u5b58\u5668\u6307\u4ee4<\/p>\n
\n\t4 #define RD_RX_PLOAD 0x61 \/\/ \u8bfb\u53d6\u63a5\u6536\u6570\u636e\u6307\u4ee4<\/p>\n
\n\t5 #define WR_TX_PLOAD 0xA0 \/\/ \u5199\u5f85\u53d1\u6570\u636e\u6307\u4ee4<\/p>\n
\n\t6 \/\/*******************SPI\uff08nRF24L01\uff09\u5bc4\u5b58\u5668\u5730\u5740<\/p>\n
\n\t7 #define CONFIG 0x00 \u3000\u3000\/\/ \u914d\u7f6e\u6536\u53d1\u72b6\u6001\uff0c<\/p>\n
\n\t8 #define EN_AA 0x01 \u3000\u3000\/\/ \u81ea\u52a8\u5e94\u7b54\u529f\u80fd\u8bbe\u7f6e<\/p>\n
\n\t9 #define EN_RXADDR 0x02 \u3000\u3000\/\/ \u53ef\u7528\u4fe1\u9053\u8bbe\u7f6e<\/p>\n
\n\t10 #define SETUP_AW 0x03 \u3000\u3000\/\/ \u6536\u53d1\u5730\u5740\u5bbd\u5ea6\u8bbe\u7f6e<\/p>\n
\n\t11 #define SETUP_RETR 0x04 \u3000\u3000\/\/ \u81ea\u52a8\u91cd\u53d1\u529f\u80fd\u8bbe\u7f6e<\/p>\n
\n\t12 #define RF_CH 0x05 \u3000\u3000\/\/ \u5de5\u4f5c\u9891\u7387\u8bbe\u7f6e<\/p>\n
\n\t13 #define RF_SETUP 0x06 \u3000\u3000\/\/ \u53d1\u5c04\u901f\u7387\u3001\u529f\u8017\u529f\u80fd\u8bbe\u7f6e<\/p>\n
\n\t14 #define STATUS 0x07 \u3000\u3000\/\/ \u72b6\u6001\u5bc4\u5b58\u5668<\/p>\n
\n\t15 #define RX_ADDR_P0 0x0A \u3000\u3000\/\/ \u9891\u90530\u63a5\u6536\u6570\u636e\u5730\u5740<\/p>\n
\n\t16 #define TX_ADDR 0x10 \u3000\u3000\/\/ \u53d1\u9001\u5730\u5740\u5bc4\u5b58\u5668<\/p>\n
\n\t17 #define RX_PW_P0 0x11 \u3000\u3000\/\/ \u63a5\u6536\u9891\u90530\u63a5\u6536\u6570\u636e\u957f\u5ea6<\/p>\n
\n\t18 #define FIF<\/u>O_STATUS 0x17 \u3000\u3000\/\/ FIFO\u6808\u5165\u6808\u51fa\u72b6\u6001\u5bc4\u5b58\u5668\u8bbe\u7f6e<\/p>\n
\n\t\u67092\u7c7b\u5bc4\u5b58\u5668\u662f\u7528\u6237\u53ef\u4ee5\u6839\u636e\u81ea\u5df1\u7684\u9700\u6c42\u6240\u786e\u5b9a\u7684\uff0c\u90a3\u5c31\u662f\u5730\u5740\u7684\u957f\u5ea6\u4ee5\u53ca\u5185\u5bb9\u3001\u53d1\u9001\u4e0e\u63a5\u6536\u6570\u636e\u7684\u957f\u5ea6\uff0c\u4f46\u65e0\u7ebf\u6a21\u5757\u4e00\u6b21\u6700\u591a\u53ef\u4ee5\u53d1\u900132\u4e2a\u5b57\u8282\uff0c\u8fd9\u4e24\u7c7b\u5bc4\u5b58\u5668\u4e00\u822c\u8bbe\u7f6e\u4e3a3~4\u4e2a\u5b57\u8282\u3002<\/p>\n
\n\t1 #define TX_PLOAD_WIDT<\/u>H 4<\/p>\n
\n\t2 #define RX_PLOAD_WIDTH 4<\/p>\n
\n\t3 unsigned char TX_ADDRESS\uff3bTX_ADR_WIDTH\uff3d= {0x34\uff0c0x43\uff0c0x10}; \/\/\u672c\u5730\u5730\u5740<\/p>\n
\n\t4 unsigned char RX_ADDRESS\uff3bRX_ADR_WIDTH\uff3d= {0x34\uff0c0x43\uff0c0x10}; \/\/\u63a5\u6536\u5730\u5740<\/p>\n
\n\tA \u6a21\u62dfSPI\u65b9\u5f0f<\/p>\n
\n\t1 \/****************************************************************************************************<\/p>\n
\n\t2 \/*\u51fd\u6570\uff1auint SPI_RW\uff08uint uchar\uff09<\/p>\n
\n\t3 \/*\u529f\u80fd\uff1aNRF24L01\u7684SPI\u65f6\u5e8f<\/p>\n
\n\t4 \/****************************************************************************************************\/<\/p>\n
\n\t5 unsigned char SPI_RW\uff08unsigned char a\uff09<\/p>\n
\n\t6 {<\/p>\n
\n\t7 unsigned char i;<\/p>\n
\n\t8 for\uff08i=0;i\u300a8;i++\uff09<\/p>\n
\n\t9 {<\/p>\n
\n\t10 if\uff08\uff08a&0x80\uff09==0x80\uff09<\/p>\n
\n\t11 MOSI=1;<\/p>\n
\n\t12 else MOSI=0; \/\/ output ‘uchar’\uff0c MSB to MOSI<\/p>\n
\n\t13 a=\uff08a\u300a\u300a1\uff09; \/\/ shift next bit into MSB.\u3002<\/p>\n
\n\t14 SCK=1; \/\/ Set SCK high.\u3002<\/p>\n
\n\t15 if\uff08MISO==1\uff09<\/p>\n
\n\t16 a|=0x01;<\/p>\n
\n\t17 else a&=0xfe; \/\/ capture current MISO bit<\/p>\n
\n\t18 SCK=0; \/\/ \u3002.then set SCK low agai<\/u>n<\/p>\n
\n\t19 }<\/p>\n
\n\t20 return\uff08a\uff09; \/\/ return read uchar<\/p>\n
\n\t21 }<\/p>\n
\n\tB \u4ee5SPI\u65b9\u5f0f\u5bf9\u5bc4\u5b58\u5668\u7684\u64cd\u4f5c<\/p>\n
\n\t1 \/****************************************************************************************************<\/p>\n
\n\t2 \/*\u51fd\u6570\uff1auchar SPI_Read\uff08uchar reg\uff09<\/p>\n
\n\t3 \/*\u529f\u80fd\uff1aNRF24L01\u7684SPI\u8bfb\u64cd\u4f5c<\/p>\n
\n\t4 \/****************************************************************************************************\/<\/p>\n
\n\t5 unsigned char SPI_Read\uff08unsigned char reg\uff09<\/p>\n
\n\t6 {<\/p>\n
\n\t7 unsigned char reg_val;<\/p>\n
\n\t8 CSN=0; \/\/ CSN low\uff0c initi<\/u>alize SPI communicaTIon.\u3002.<\/p>\n
\n\t9 SPI_RW\uff08reg\uff09; \/\/ Select register to read from<\/u>.\u3002<\/p>\n
\n\t10 reg_val=SPI_RW\uff080\uff09; \/\/ \u3002.then read registervalue<\/p>\n
\n\t11 CSN=1; \/\/ CSN high\uff0c terminate SPI communicaTIon<\/p>\n
\n\t12 return\uff08reg_val\uff09; \/\/ return register value<\/p>\n
\n\t13 }<\/p>\n
\n\t14 \/****************************************************************************************************\/<\/p>\n
\n\t15 \/*\u529f\u80fd\uff1aNRF24L01\u8bfb\u5199\u5bc4\u5b58\u5668\u51fd\u6570<\/p>\n
\n\t16 \/****************************************************************************************************\/<\/p>\n
\n\t17 unsigned char SPI_RW_Reg\uff08unsigned char reg\uff0c unsigned char value\uff09<\/p>\n
\n\t18 {<\/p>\n
\n\t19 unsigned char status;<\/p>\n
\n\t20 CSN = 0; \/\/ CSN low\uff0c init SPI transacTIon<\/p>\n
\n\t21 status=SPI_RW\uff08reg\uff09; \/\/ select register<\/p>\n
\n\t22 SPI_RW\uff08value\uff09; \/\/ \u3002.and write value to it.\u3002<\/p>\n
\n\t23 CSN = 1; \/\/ CSN high again<\/p>\n
\n\t24 return\uff08status\uff09; \/\/ return nRF24L01 status uchar<\/p>\n
\n\t25 }<\/p>\n
\n\t26 \/****************************************************************************************************\/<\/p>\n
\n\t27 \/*\u51fd\u6570\uff1auint SPI_Read_Buf\uff08uchar reg\uff0c uchar *pBuf\uff0c uchar uchars<\/u>\uff09<\/p>\n
\n\t28 \/*\u529f\u80fd\uff1a \u7528\u4e8e\u8bfb\u6570\u636e\uff0creg\uff1a\u4e3a\u5bc4\u5b58\u5668\u5730\u5740\uff0cpBuf\uff1a\u4e3a\u5f85\u8bfb\u51fa\u6570\u636e\u5730\u5740\uff0cuchars\uff1a\u8bfb\u51fa\u6570\u636e\u7684\u4e2a\u6570<\/p>\n
\n\t29 \/****************************************************************************************************\/<\/p>\n
\n\t30 unsigned char SPI_Read_Buf\uff08unsigned char reg\uff0c unsigned char *pBuf\uff0c unsigned char uchars\uff09<\/p>\n
\n\t31 {<\/p>\n
\n\t32 unsigned char status\uff0cuchar_ctr;<\/p>\n
\n\t33 CSN = 0; \/\/ Set CSN low\uff0c init SPI tranacTIon<\/p>\n
\n\t34 status=SPI_RW\uff08reg\uff09; \/\/ Select register to write to and read status uchar<\/p>\n
\n\t35<\/p>\n
\n\t36 for\uff08uchar_ctr=0;uchar_ctr<\/p>\n
\n\t37 {<\/p>\n
\n\t38 pBuf\uff3buchar_ctr\uff3d=SPI_RW\uff080\uff09;<\/p>\n
\n\t39 }<\/p>\n
\n\t40 CSN = 1;<\/p>\n
\n\t41<\/p>\n
\n\t42 re<\/p>\n","protected":false},"excerpt":{"rendered":"
\u5148\u7b80\u5355\u7684\u4ecb\u7ecd\u4e0bn RF 2 4L 01\u65e0\u7ebf\u6a21\u5757 \uff081\uff09 2.4Ghz \u5168\u7403\u5f00\u653eISM \u9891\u6bb5\u514d\u8bb8\u53ef\u8bc1\u4f7f\u7528 \uff082\uff09 \u6700\u9ad8\u5de5\u4f5c\u901f\u73872Mbps\uff0c\u9ad8\u6548GFSK\u8c03\u5236\uff0c\u6297\u5e72\u6270\u80fd\u529b\u5f3a\uff0c\u7279\u522b\u9002\u5408\u5de5\u4e1a\u63a7\u5236\u573a\u5408 \uff083\uff09 126 \u9891\u9053\uff0c\u6ee1\u8db3\u591a\u70b9\u901a<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[14],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2911"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2911"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2911\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2911"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2911"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2911"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}