![\"STM32\u5355\u7247\u673a\u5b9e\u73b0\u76f4\u6d41\u51cf\u901f\u7535\u673a\u63a7\u5236\u7684\u7a0b\u5e8f\u8bbe\u8ba1\"](\"http:\/\/www.szryc.com\/uploads\/allimg\/191028\/2203153318-0.png\")
\n\t <\/p>\n
\n\t\u5728\u76f4\u6d41\u51cf\u901f\u7535\u673a\u63a7\u5236\u4e2d\uff0c\u6700\u5e38\u7528\u7684\u65b9\u6cd5\u5c31\u662f\u901a\u8fc7PWM\u6765\u63a7\u5236\u76f4\u6d41\u7535\u673a\u7684\u8f6c\u901f\u3002\u5728\u63a7\u5236\u5c0f\u8f66\u8d70\u76f4\u7ebf\u7684\u8fc7\u7a0b\u4e2d\uff0c\u9700\u8981\u4e24\u8005\u7684\u8f6c\u901f\u4e00\u7f6e\uff08\u5982\u679c\u8981\u8d70\u5f97\u5f88\u76f4\uff0c\u8fd8\u9700\u8981\u5728\u77ed\u65f6\u95f4\u5185\u4fdd\u8bc1\u4e24\u8005\u7684\u884c\u7a0b\u5927\u81f4\u76f8\u5f53\uff0c\u8fd9\u53ef\u4ee5\u7528PI<\/u>D\u7b97\u6cd5\u6765\u63a7\u5236\uff09\u3002\u56e0\u6b64\uff0c\u5728\u68c0\u6d4b\u5230\u4e24\u8005\u8f6c\u901f\u4e0d\u4e00\u6837\u65f6\uff0c\u9700\u8981\u52a8\u6001\u8c03\u6574\u5176\u4e2d\u4e00\u4e2a\u6216\u4e24\u4e2a\u8f6e\u5b50\u7684PWM\u7684\u70b9\u7a7a\u6bd4\uff08\u7b80\u5355\u70b9\u7684\u5c31\u4ee5\u4e00\u4e2a\u8f6e\u4e3a\u57fa\u51c6\uff0c\u8c03\u6574\u53e6\u5916\u4e00\u4e2a\u8f6e\u5b50\u5373\u53ef\uff1b\u5982\u679c\u4ee5\u4e00\u4e2a\u56fa\u5b9a\u7684\u6807\u51c6\u7684\u8bdd\uff0c\u9700\u8981\u8c03\u6574\u4e24\u4e2a\u8f6e\u5b50\u7684PWM\u5360\u7a7a\u6bd4\uff09\u3002<\/p>\n
\n\t
\n\t <\/p>\n
\n\t1 \u7a0b\u5e8f\u7b2c\u4e00\u6b65\uff1a\u8bbe\u7f6eGPIO\uff0c\u7565\uff08\u8f93\u51faPWM\u7684\u7ba1\u811a\u7528Mode_AF_PP\u5373\u53ef\uff09<\/p>\n
\n\t2<\/p>\n
\n\t3 \u7a0b\u5e8f\u7b2c\u4e8c\u6b65\uff1a\u8bbe\u7f6e\u5b9a\u65f6\u5668<\/u>\uff0c\uff08\u4fdd\u8bc1\u4ea7\u751f\u4e24\u8defPWM\u5373\u53ef\uff0c\u6211\u7528\u7684\u662fTI<\/u>M4\uff09<\/p>\n
\n\t4<\/p>\n
\n\t5 void TIM4_ConfiguraTIon\uff08void\uff09<\/p>\n
\n\t6 {<\/p>\n
\n\t7 TIM_TImeBaseInitTypeDef TIM_TimeBaseInitStructure;<\/p>\n
\n\t8 TIM_OCInitTypeDef TIM_OCInitStructure;<\/p>\n
\n\t9<\/p>\n
\n\t10 \/\/\u65f6\u95f4\u57fa\u521d\u59cb\u5316<\/p>\n
\n\t11 TIM_TimeBaseInitStructure.TIM_Period=144; \/\/18K\/144=125Hz\uff0c\u8fd9\u4e2a\u662f\u7535\u673aPWM\u7684\u9891\u7387<\/p>\n
\n\t12 TIM_TimeBaseInitStructure.TIM_Prescaler=4000; \/\/72000000\/4000=18K<\/p>\n
\n\t13 TIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;<\/p>\n
\n\t14 TIM_TimeBaseInitStructure.TIM_Counte<\/u>rMode=TIM_CounterMode_Up;<\/p>\n
\n\t15 TIM_TimeBaseInitStructure.TIM_RepetitionCounter=0x0000;<\/p>\n
\n\t16<\/p>\n
\n\t17 TIM_TimeBaseInit\uff08TIM4\uff0c&TIM_TimeBaseInitStructure\uff09;<\/p>\n
\n\t18<\/p>\n
\n\t19 \/\/\u8f93\u51fa\u6bd4\u8f83\u6a21\u5f0f\u8bbe\u7f6e\uff0c\u7528\u4e8e4\u8defPWM\u8f93\u51fa<\/p>\n
\n\t20 TIM_OCInitStructure.TIM_OCMode=TIM_OCMode_PWM2; \/\/\u8f93\u51faPWM<\/p>\n
\n\t21 TIM_OCInitStructure.TIM_OutputState=TIM_OutputState_Enable; \/\/\u4f7f\u80fd\u6b63\u5411\u901a\u9053<\/p>\n
\n\t22 TIM_OCInitStructure.TIM_OutputNState=TIM_OutputState_Disable; \/\/\u5931\u80fd\u53cd\u5411\u901a\u9053<\/p>\n
\n\t23 TIM_OCInitStructure.TIM_Pulse=PWM_L; \/\/\u5de6\u8f6eDIR\u7684\u5360\u7a7a\u6bd4<\/p>\n
\n\t24 TIM_OCInitStructure.TIM_OCPolarity=TIM_OCPolarity_Low; \/\/\u8f93\u51fa\u6781\u6027\u4e3a\u4f4e\u7535\u5e73<\/p>\n
\n\t25 TIM_OCInitStructure.TIM_OCNPolarity=TIM_OCPolarity_High;\/\/\u4e92\u8865\u8f93\u51fa\u6781\u6027\u4e3a\u9ad8\u7535\u5e73<\/p>\n
\n\t26 TIM_OCInitStructure.TIM_OCIdleState=TIM_OCIdleState_Set;<\/p>\n
\n\t27 TIM_OCInitStructure.TIM_OCNIdleState=TIM_OCNIdleState_Reset;<\/p>\n
\n\t28<\/p>\n
\n\t29 TIM_OC1Init\uff08TIM4\uff0c&TIM_OCInitStructure\uff09; \/\/PWM_L\u521d\u59cb\u5316<\/p>\n
\n\t30 TIM_OC1PreloadC<\/u>onfig\uff08TIM4\uff0cTIM_OCPreload_Disable\uff09; \/\/\u6539\u53d8\u70b9\u7a7a\u6bd4\u540e\uff0c\u7acb\u5373\u4ea7\u751f\u6548\u5e94<\/p>\n
\n\t31<\/p>\n
\n\t32 TIM_OCInitStructure.TIM_Pulse=PWM_R; \/\/\u5de6\u8f6ePWM\u7684\u5360\u7a7a\u6bd4<\/p>\n
\n\t33 TIM_OC2Init\uff08TIM4\uff0c&TIM_OCInitStructure\uff09; \/\/PWM_R\u521d\u59cb\u5316<\/p>\n
\n\t34 TIM_OC2PreloadConfig\uff08TIM4\uff0cTIM_OCPreload_Disable\uff09; \/\/\u6539\u53d8\u70b9\u7a7a\u6bd4\u540e\uff0c\u7acb\u5373\u4ea7\u751f\u6548\u5e94<\/p>\n
\n\t35<\/p>\n
\n\t36 \/\/\u4f7f\u80fd\u5b9a\u65f6\u56684<\/p>\n
\n\t37 TIM_Cmd\uff08TIM4\uff0cENABLE\uff09;<\/p>\n
\n\t38 TIM_CtrlPWMOutputs\uff08TIM4\uff0cENABLE\uff09;<\/p>\n
\n\t\u7a0b\u5e8f\u7b2c\u4e00\u6b65\uff1a\u8bbe\u7f6eGPIO\uff0c\u7565\uff08\u8f93\u51faPWM\u7684\u7ba1\u811a\u7528Mode_AF_PP\u5373\u53ef\uff09<\/p>\n
\n\t\u7a0b\u5e8f\u7b2c\u4e8c\u6b65\uff1a\u8bbe\u7f6e\u5b9a\u65f6\u5668\uff0c\uff08\u4fdd\u8bc1\u4ea7\u751f\u4e24\u8defPWM\u5373\u53ef\uff0c\u6211\u7528\u7684\u662fTIM4\uff09<\/p>\n
\n\tvoid TIM4_Configuration\uff08void\uff09<\/p>\n
\n\t{<\/p>\n
\n\tTIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;<\/p>\n
\n\tTIM_OCInitTypeDef TIM_OCInitStructure;<\/p>\n
\n\t\/\/\u65f6\u95f4\u57fa\u521d\u59cb\u5316<\/p>\n
\n\tTIM_TimeBaseInitStructure.TIM_Period=144; \/\/18K\/144=125Hz\uff0c\u8fd9\u4e2a\u662f\u7535\u673aPWM\u7684\u9891\u7387<\/p>\n
\n\tTIM_TimeBaseInitStructure.TIM_Prescaler=4000; \/\/72000000\/4000=18K<\/p>\n
\n\tTIM_TimeBaseInitStructure.TIM_ClockDivision=TIM_CKD_DIV1;<\/p>\n
\n\tTIM_TimeBaseInitStructure.TIM_CounterMode=TIM_CounterMode_Up;<\/p>\n
\n\tTIM_TimeBaseInitStructure.TIM_RepetitionCounter=0x0000;<\/p>\n
\n\tTIM_TimeBaseInit\uff08TIM4\uff0c&TIM_TimeBaseInitStructure\uff09;<\/p>\n
\n\t\/\/\u8f93\u51fa\u6bd4\u8f83\u6a21\u5f0f\u8bbe\u7f6e\uff0c\u7528\u4e8e4\u8defPWM\u8f93\u51fa<\/p>\n
\n\tTIM_OCInitStructure.TIM_OCMode=TIM_OCMode_PWM2; \/\/\u8f93\u51faPWM<\/p>\n
\n\tTIM_OCInitStructure.TIM_OutputState=TIM_OutputState_Enable; \/\/\u4f7f\u80fd\u6b63\u5411\u901a\u9053<\/p>\n
\n\tTIM_OCInitStructure.TIM_OutputNState=TIM_OutputState_Disable; \/\/\u5931\u80fd\u53cd\u5411\u901a\u9053<\/p>\n
\n\tTIM_OCInitStructure.TIM_Pulse=PWM_L; \/\/\u5de6\u8f6eDIR\u7684\u5360\u7a7a\u6bd4<\/p>\n
\n\tTIM_OCInitStructure.TIM_OCPolarity=TIM_OCPolarity_Low; \/\/\u8f93\u51fa\u6781\u6027\u4e3a\u4f4e\u7535\u5e73<\/p>\n
\n\tTIM_OCInitStructure.TIM_OCNPolarity=TIM_OCPolarity_High;\/\/\u4e92\u8865\u8f93\u51fa\u6781\u6027\u4e3a\u9ad8\u7535\u5e73<\/p>\n
\n\tTIM_OCInitStructure.TIM_OCIdleState=TIM_OCIdleState_Set;<\/p>\n
\n\tTIM_OCInitStructure.TIM_OCNIdleState=TIM_OCNIdleState_Reset;<\/p>\n
\n\tTIM_OC1Init\uff08TIM4\uff0c&TIM_OCInitStructure\uff09; \/\/PWM_L\u521d\u59cb\u5316<\/p>\n
\n\tTIM_OC1PreloadConfig\uff08TIM4\uff0cTIM_OCPreload_Disable\uff09; \/\/\u6539\u53d8\u70b9\u7a7a\u6bd4\u540e\uff0c\u7acb\u5373\u4ea7\u751f\u6548\u5e94<\/p>\n
\n\tTIM_OCInitStructure.TIM_Pulse=PWM_R; \/\/\u5de6\u8f6ePWM\u7684\u5360\u7a7a\u6bd4<\/p>\n
\n\tTIM_OC2Init\uff08TIM4\uff0c&TIM_OCInitStructure\uff09; \/\/PWM_R\u521d\u59cb\u5316<\/p>\n
\n\tTIM_OC2PreloadConfig\uff08TIM4\uff0cTIM_OCPreload_Disable\uff09; \/\/\u6539\u53d8\u70b9\u7a7a\u6bd4\u540e\uff0c\u7acb\u5373\u4ea7\u751f\u6548\u5e94<\/p>\n
\n\t\/\/\u4f7f\u80fd\u5b9a\u65f6\u56684<\/p>\n
\n\tTIM_Cmd\uff08TIM4\uff0cENABLE\uff09;<\/p>\n
\n\tTIM_CtrlPWMOutputs\uff08TIM4\uff0cENABLE\uff09;<\/p>\n
\n\t1 \u7a0b\u5e8f\u7b2c\u4e09\u6b65\uff1a<\/p>\n
\n\t2<\/p>\n
\n\t3 \u5728SysTick\u4e2d\u65ad\u4e2d\uff0c\u8bfb\u53d6\u4e24\u4e2a\u8f6e\u5b50\u7684\u901f\u5ea6\uff08\u5177\u4f53\u7684\u65b9\u6cd5\u662f\uff1a\u6bcf0.1\u79d2\u8bfb\u4e00\u6b21\uff0c\u5e76\u4ee5\u6b64\u4eba\u4f5c\u4e3a\u901f\u5ea6\u7684\u4f9d\u636e\uff09\uff0c\u5e76\u6bd4\u8f83\uff0c\u5982\u679c\u4ee5\u53f3\u8f6e\u4e3a\u57fa\u51c6\uff0c\u5219\u8c03\u6574\u5de6\u8f6e\u7684PWM\u5360\u7a7a\u6bd4\u3002\u6d89\u53ca\u5230\u5173\u952e\u8bed\u53e5\u662f\uff1aTIM_SetCompare1\uff08\uff09\uff1b<\/p>\n
\n\t4<\/p>\n
\n\t5 u16 COUN1=0;<\/p>\n
\n\t6 u16 COUN2=0;<\/p>\n
\n\t7<\/p>\n
\n\t8 volatile u16 Dist_L=0; \/\/\u5de6\u8f6e\u884c\u7a0b\u8109\u51b2\u6570<\/p>\n
\n\t9 volatile u16 Dist_R=0; \/\/\u53f3\u8f6e\u884c\u7a0b\u8109\u51b2\u6570<\/p>\n
\n\t10 void SysTick_Handler\uff08void\uff09<\/p>\n
\n\t11 {<\/p>\n
\n\t12<\/p>\n
\n\t13 \u3000\u3000COUN1=TIM1-\u300bCNT; \/\/\u5de6\u8f6e\u57280.1\u79d2\u91cc\u8109\u51b2\u6570<\/p>\n
\n\t14 \u3000\u3000COUN2=TIM2-\u300bCNT; \/\/\u53f3\u8f6e\u57280.1\u79d2\u91cc\u8109\u51b2\u6570<\/p>\n
\n\t15 \u3000\u3000Dist_L=Dist_L+COUN1; \/\/\u5de6\u8f6e\u884c\u7a0b\u8109\u51b2\u6570<\/p>\n
\n\t16 \u3000\u3000Dist_R=Dist_R+COUN2; \/\/\u53f3\u8f6e\u884c\u7a0b\u8109\u51b2\u6570<\/p>\n
\n\t17 \u3000\u3000if<\/u>\uff08 \uff08COUN1-COUN2\uff09\u300b2\uff09<\/p>\n
\n\t18 \u3000\u3000{<\/p>\n
\n\t19 \u3000\u3000 PWM_L= TIM_GetCapture1\uff08TIM4\uff09;<\/p>\n
\n\t20 \u3000 \u3000TIM_SetCompare1\uff08TIM4\uff0c PWM_L - 4\uff09;<\/p>\n
\n\t21 \u3000\u3000}<\/p>\n
\n\t22 else if \uff08 \uff08COUN2-COUN1\uff09\u300b2\uff09<\/p>\n
\n\t23 {<\/p>\n
\n\t24 PWM_L= TIM_GetCapture1\uff08TIM4\uff09;<\/p>\n
\n\t25 TIM_SetCompare1\uff08TIM4\uff0c PWM_L + 4\uff09;<\/p>\n
\n\t26 }<\/p>\n
\n\t27<\/p>\n
\n\t28 TIM_SetCounter\uff08TIM1\uff0c 0\uff09;<\/p>\n
\n\t29 TIM_SetCounter\uff08TIM2\uff0c 0\uff09;<\/p>\n
\n\t30<\/p>\n
\n\t31 }<\/p>\n
\n\t32<\/p>\n
\n\t33 \u5173\u4e8eTIM_SetCompareX\uff08\uff1b\uff09\u8fd9\u4e2a\u51fd\u6570\uff0c\u8fd8\u662f\u6709\u5f88\u591a\u7528\u9014\u7684\uff0c\u5176\u4e2d\u53e6\u5916\u4e00\u4e2a\u7528\u9014\uff0c\u5c31\u662f\u7528\u4e8e\u4ea7\u751f\u4e0d\u540c\u9891\u7387\u7684PWM\uff0c\u5177\u4f53\u7a0b\u5e8f\u5982\u4e0b\uff1a<\/p>\n
\n\t34<\/p>\n
\n\t35 u16 capture = 0;<\/p>\n
\n\t36<\/p>\n
\n\t37 extern vu16 CCR1_Val;<\/p>\n
\n\t38 extern vu16 CCR2_Val;<\/p>\n
\n\t39 extern vu16 CCR3_Val;<\/p>\n
\n\t40 extern vu16 CCR4_Val;<\/p>\n
\n\t41<\/p>\n
\n\t42 void TIM2_IRQHandler\uff08void\uff09<\/p>\n
\n\t43 {<\/p>\n
\n\t44<\/p>\n
\n\t45 \/* TIM2_CH1 toggling with frequency = 183.1 Hz *\/<\/p>\n
\n\t46 if \uff08TIM_GetITStatus\uff08TIM2\uff0c TIM_IT_CC1\uff09 \uff01= RESET\uff09<\/p>\n
\n\t47 {<\/p>\n
\n\t48 TIM_ClearITPendingBit\uff08TIM2\uff0c TIM_IT_CC1 \uff09;<\/p>\n
\n\t49 \u3000\u3000capture = TIM_GetCapture1\uff08TIM2\uff09;<\/p>\n
\n\t50 \u3000\u3000TIM_SetCompare1\uff08TIM2\uff0c capture + CCR1_Val \uff09;<\/p>\n
\n\t51 }<\/p>\n
\n\t52<\/p>\n
\n\t53 \/* TIM2_CH2 toggling with frequency = 366.2 Hz *\/<\/p>\n
\n\t54 if \uff08TIM_GetITStatus\uff08TIM2\uff0c TIM_IT_CC2\uff09 \uff01= RESET\uff09<\/p>\n
\n\t55 {<\/p>\n
\n\t56 TIM_ClearITPendingBit\uff08TIM2\uff0c TIM_IT_CC2\uff09;<\/p>\n
\n\t57 \u3000\u3000capture = TIM_GetCapture2\uff08TIM2\uff09;<\/p>\n
\n\t58 TIM_SetCompare2\uff08TIM2\uff0c capture + CCR2_Val\uff09;<\/p>\n
\n\t59 }<\/p>\n
\n\t60<\/p>\n
\n\t61 \/* TIM2_CH3 toggling with frequency = 732.4 Hz *\/<\/p>\n
\n\t62 if \uff08TIM_GetITStatus\uff08TIM2\uff0c TIM_IT_CC3\uff09 \uff01= RESET\uff09<\/p>\n
\n\t63 {<\/p>\n
\n\t64 TIM_ClearITPendingBit\uff08TIM2\uff0c TIM_IT_CC3\uff09;<\/p>\n
\n\t65 \u3000\u3000capture = TIM_GetCapture3\uff08TIM2\uff09;<\/p>\n
\n\t66 TIM_SetCompare3\uff08TIM2\uff0c capture + CCR3_Val\uff09;<\/p>\n
\n\t67 }<\/p>\n
\n\t68<\/p>\n
\n\t69 \/* TIM2_CH4 toggling with frequency = 1464.8 Hz *\/<\/p>\n
\n\t70 if \uff08TIM_GetITStatus\uff08TIM2\uff0c TIM_IT_CC4\uff09 \uff01= RESET\uff09<\/p>\n
\n\t71 {<\/p>\n
\n\t72 TIM_ClearITPendingBit\uff08TIM2\uff0c TIM_IT_CC4\uff09;<\/p>\n
\n\t73 \u3000\u3000capture = TIM_GetCapture4\uff08TIM2\uff09;<\/p>\n
\n\t74 TIM_SetCompare4\uff08TIM2\uff0c capture + CCR4_Val\uff09;<\/p>\n
\n\t75 }<\/p>\n
\n\t76<\/p>\n
\n\t77 }
\n\t\u6765\u6e90\uff1b21ic<\/p>\n","protected":false},"excerpt":{"rendered":"
\u5728\u76f4\u6d41\u51cf\u901f\u7535\u673a\u63a7\u5236\u4e2d\uff0c\u6700\u5e38\u7528\u7684\u65b9\u6cd5\u5c31\u662f\u901a\u8fc7PWM\u6765\u63a7\u5236\u76f4\u6d41\u7535\u673a\u7684\u8f6c\u901f\u3002\u5728\u63a7\u5236\u5c0f\u8f66\u8d70\u76f4\u7ebf\u7684\u8fc7\u7a0b\u4e2d\uff0c\u9700\u8981\u4e24\u8005\u7684\u8f6c\u901f\u4e00\u7f6e\uff08\u5982\u679c\u8981\u8d70\u5f97\u5f88\u76f4\uff0c\u8fd8\u9700\u8981\u5728\u77ed\u65f6\u95f4\u5185\u4fdd\u8bc1\u4e24\u8005\u7684\u884c\u7a0b\u5927\u81f4<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[12],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2864"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2864"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2864\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2864"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2864"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2864"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}