{"id":2783,"date":"2019-08-30T08:13:18","date_gmt":"2019-08-30T08:13:18","guid":{"rendered":""},"modified":"2019-08-30T16:13:35","modified_gmt":"2019-08-30T08:13:35","slug":"%e8%8b%b1%e7%89%b9%e5%b0%94%e5%8f%91%e5%b8%83fpga%e6%96%b0%e5%93%81+%e9%9b%86%e6%88%90hbm2%e5%86%85%e5%ad%98%e6%9b%b4%e4%ba%ae%e7%9c%bc","status":"publish","type":"post","link":"http:\/\/www.szryc.com\/?p=2783","title":{"rendered":"\u82f1\u7279\u5c14\u53d1\u5e03FPGA\u65b0\u54c1 \u96c6\u6210HBM2\u5185\u5b58\u66f4\u4eae\u773c"},"content":{"rendered":"

\n\t\u82f1\u7279\u5c14<\/u>\u6700\u65b0\u53d1\u5e03\u4e86\u4e00\u6b3eFPGA<\/u>\u4ea7\u54c1Intel<\/u> Strati<\/u>x 10 MX FPGA\u3002\u4f5c\u4e3aStraTIx 10\u4ea7\u54c1\u7ebf\u7684\u4e00\u90e8\u5206\uff0c\u5b83\u62e5\u6709\u4e00\u4e2a\u9ad8\u6027\u80fd(\u6765\u81eaAltera<\/u>)FPGA\u677f\u8f7d\u3002\u66f4\u503c\u5f97\u6211\u4eec\u5173\u6ce8\u7684\u662f\uff0c\u5b83\u5177\u6709\u9ad8\u5e26\u5bbd\u5185\u5b58DRAM<\/u>(HBM2)\u96c6\u6210\u3002\u5c06HBM2\u4e0eFPGA\u96c6\u6210\u5728\u4e00\u8d77\uff0c\u89e3\u51b3\u4e86\u8bb8\u591a\u516c\u53f8\u5bf9FPGA\u3001\u5185\u5b58\u5e26\u5bbd\u9700\u6c42\u53ca\u5e94\u7528\u7684\u4e3b\u8981\u74f6\u9888\u3002\u4f7f\u7528HBM2 \u7684Inte<\/u>l StraTIx 10 MX\u5185\u5b58\u5e26\u5bbd\u9ad8\u8fbe512GB\/s\uff0c\u8fd9\u6837\u7684\u6027\u80fd\uff0c\u8ba9\u4eba\u5f88\u96be\u5c06\u76ee\u5149\u4ece\u5b83\u8eab\u4e0a\u79fb\u5f00\u3002<\/p>\n

\n\t\u5728\u5e02\u573a\u7ec6\u5206\u65b9\u9762\uff0cHBM2\u7684Intel StraTIx 10 MX FPGA\u9488\u5bf9HPC\u548c\u5927\u6570\u636e<\/u>\u5206\u6790\u5de5\u4f5c\u8d1f\u8f7d(\u5982Apache Spark\u6d41)\uff0c\u53ef\u4ee5\u538b\u7f29\u3001\u52a0\u5bc6\u3001\u89e3\u5bc6\u548c\u52a0\u901f\u6570\u636e\u96c6\u3002\u4f7f\u7528FPGA\u52a0\u901f\uff0c\u53ef\u83b7\u5f97\u66f4\u9ad8\u7684\u8ba1\u7b97\u80fd\u529b\u3002<\/p>\n

\n\t <\/div>\n

\n\t\"\u82f1\u7279\u5c14\u53d1\u5e03FPGA\u65b0\u54c1<\/p>\n

\n\t\u5c06FPGA\u7845\u4e0eHBM2\u96c6\u6210\uff0c\u4f7f\u7528\u4e86\u82f1\u7279\u5c14\u7684\u5d4c\u5165\u5f0f\u591a\u88f8\u7247\u4e92\u8fde\u6865\u63a5(EMI<\/u>B)\u6280\u672f\u3002\u8fd9\u610f\u5473\u7740\u82f1\u7279\u5c14\u5df2\u80fd\u591f\u901a\u8fc7\u5f02\u6784\u7ed3\u6784\u4f7f\u7528\u5c01\u88c5\u5fae\u51f8\u5757(micro-bumps<\/u>)\u6765\u63d0\u4f9b\u9ad8\u901f\u94fe\u63a5\u3002\u82f1\u7279\u5c14\u7684StraTIx 10\u4ea7\u54c1\u7ebf\u5efa\u7acb\u5728\u5b83\u768414nm\u5236\u7a0b\u4e4b\u4e0a\uff0c\u800c\u4e14\u82f1\u7279\u5c14\u53ef\u4ee5\u4f7f\u7528EMIB\u5c06\u975e\u82f1\u7279\u5c14\u7ec4\u4ef6(\u4f8b\u5982HBM2)\u96c6\u6210\u5230\u4e00\u4e2a\u9ad8\u901f\u7684\u4e92\u8fde\u4e0a\u3002<\/p>\n

\n\t\u5728\u6211\u4eec\u770b\u6765\uff0cEMIB\u662f\u4e00\u9879\u91cd\u8981\u7684\u652f\u6301\u6280\u672f\uff0c\u5b83\u4f1a\u8ba9\u82f1\u7279\u5c14(\u4ee5\u53ca\u5176\u4ed6\u62e5\u6709\u8be5\u540c\u7c7b\u578b\u6280\u672f\u7684\u4f01\u4e1a)\u5728\u672a\u6765\u5236\u9020<\/u>\u51fa\u66f4\u5f3a\u7684\u8ba1\u7b97\u5e73\u53f0\u3002\u5c31\u76ee\u524d\u6765\u8bf4\uff0cIntel Stratix 10 MX FPGA\u4ea7\u54c1\u7684\u51fa\u73b0\u5bf9\u8be5\u6280\u672f\u7684\u53d1\u5c55\u4e5f\u5177\u6709\u91cd\u8981\u8c61\u5f81\u610f\u4e49\u3002\u8bf8\u5982\u82f1\u7279\u5c14X86\u4e0eEMIB\u6280\u672f\u76f8\u7ed3\u5408\u7684\u67b6\u6784\uff0c\u672a\u6765\u53ef\u7528\u4e8e\u96c6\u6210\u5404\u79cd\u4f18\u79c0\u7684\u5185\u5b58\u6280\u672f\u6216\u52a0\u901f\u5668\u3002\u9664\u6b64\u4e4b\u5916\uff0c\u5b83\u8fd8\u53ef\u4ee5\u7528\u6765\u5c06\u8bb8\u591aX86\u8ba1\u7b97\u8d44\u6e90\u6574\u5408\u5230\u4e00\u4e2a\u5355\u4e00\u7684\u5305\u4e2d\uff0c\u540c\u65f6\u4fdd\u6301\u66f4\u9ad8\u7684\u6536\u76ca\u3002<\/p>\n

\n\tFPGA\u884c\u4e1a\u662f\u975e\u5e38\u4e13\u6709\u5316\u7684\uff0c\u4f46\u662fEMIB\u6280\u672f\u8ba9\u6211\u4eec\u770b\u5230\u4e86\u66f4\u591a\u7684\u53ef\u80fd\u6027\uff0c\u4e5f\u62d3\u5bbd\u4e86\u672a\u6765\u7684\u9053\u8def\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"

\u82f1\u7279\u5c14 \u6700\u65b0\u53d1\u5e03\u4e86\u4e00\u6b3e FPGA \u4ea7\u54c1 Intel Stra ti x 10 MX FPGA\u3002\u4f5c\u4e3aStraTIx 10\u4ea7\u54c1\u7ebf\u7684\u4e00\u90e8\u5206\uff0c\u5b83\u62e5\u6709\u4e00\u4e2a\u9ad8\u6027\u80fd(\u6765\u81ea Altera )FPGA\u677f\u8f7d\u3002\u66f4\u503c\u5f97\u6211\u4eec\u5173\u6ce8\u7684\u662f\uff0c\u5b83\u5177\u6709\u9ad8\u5e26\u5bbd\u5185\u5b58 DRAM (HBM2)\u96c6\u6210\u3002\u5c06<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[14],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2783"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2783"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2783\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2783"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2783"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2783"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}