{"id":1003,"date":"2018-09-18T15:33:25","date_gmt":"2018-09-18T15:33:25","guid":{"rendered":""},"modified":"2018-09-18T23:28:59","modified_gmt":"2018-09-18T15:28:59","slug":"%e4%ba%86%e8%a7%a3%e9%9b%86%e6%88%90%e5%bc%8f%e5%b5%8c%e5%85%a5%e5%bc%8f%e8%a7%86%e8%a7%89%e5%b9%b3%e5%8f%b0%e5%ba%94%e7%94%a8%e8%ae%be%e8%ae%a1","status":"publish","type":"post","link":"http:\/\/www.szryc.com\/?p=1003","title":{"rendered":"\u4e86\u89e3\u96c6\u6210\u5f0f\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e73\u53f0\u5e94\u7528\u8bbe\u8ba1"},"content":{"rendered":"

\n\t\u968f\u7740\u6444\u50cf\u5934\u548c\u5176\u4ed6\u8bbe\u5907\u4ea7\u751f\u7684\u6570\u636e\u5728\u5feb\u901f\u589e\u957f\uff0c\u4fc3\u4f7f\u4eba\u4eec\u8fd0\u7528\u673a\u5668\u5b66\u4e60<\/u>\u4ece\u6c7d\u8f66\u3001\u5b89\u9632\u548c\u5176\u4ed6\u5e94\u7528\u4ea7\u751f\u7684\u5f71\u50cf\u4e2d\u63d0\u53d6\u66f4\u591a\u6709\u7528\u7684\u4fe1\u606f\u3002\u4e13\u7528\u5668\u4ef6\u6709\u671b\u5728\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94\u7528\u4e2d\u5b9e\u73b0\u9ad8\u6027\u80fd\u673a\u5668\u5b66\u4e60 (ML) \u63a8\u7406\u3002\u4f46\u662f\u6b64\u7c7b\u5668\u4ef6\u5927\u90fd\u5904\u4e8e\u65e9\u671f\u5f00\u53d1\u9636\u6bb5\uff0c\u56e0\u4e3a\u8bbe\u8ba1\u4eba\u5458\u6b63\u5728\u52aa\u529b\u5bfb\u627e\u6700\u6709\u6548\u7684\u7b97\u6cd5\uff0c\u751a\u81f3\u4eba\u5de5\u667a\u80fd (AI<\/u>) \u7814\u7a76\u4eba\u5458\u4e5f\u5728\u8fc5\u901f\u63a8\u6f14\u65b0\u65b9\u6cd5\u3002<\/p>\n

\n\t\u76ee\u524d\uff0c\u5f00\u53d1\u4eba\u5458\u4e00\u822c\u4f7f\u7528\u9488\u5bf9 ML \u7684\u53ef\u7528 FPGA \u5e73\u53f0\u6765\u6784\u5efa\u5d4c\u5165\u5f0f\u89c6\u89c9\u7cfb\u7edf\uff0c\u4ee5\u671f\u6ee1\u8db3\u66f4\u9ad8\u7684\u6027\u80fd\u8981\u6c42\u3002\u4e0e\u6b64\u540c\u65f6\uff0c\u4ed6\u4eec\u53ef\u4ee5\u4fdd\u6301\u6240\u9700\u7684\u7075\u6d3b\u6027\uff0c\u4ee5\u8ddf\u4e0a\u673a\u5668\u5b66\u4e60\u53d1\u5c55\u7684\u6b65\u4f10\u3002<\/p>\n

\n\t <\/div>\n

\n\t\u672c\u6587\u5c06\u4ecb\u7ecd ML \u5904\u7406\u7684\u8981\u6c42\uff0c\u4ee5\u53ca\u4e3a\u4f55 FPGA \u80fd\u89e3\u51b3\u8bb8\u591a\u6027\u80fd\u95ee\u9898\u3002\u7136\u540e\uff0c\u5c06\u4ecb\u7ecd\u4e00\u4e2a\u5408\u9002\u7684\u57fa\u4e8e FPGA \u7684 ML \u5e73\u53f0\u53ca\u5176\u4f7f\u7528\u65b9\u6cd5\u3002<\/p>\n

\n\t\u673a\u5668\u5b66\u4e60\u7b97\u6cd5\u548c\u63a8\u7406\u5f15\u64ce<\/h2>\n

\n\t\u5728 ML \u7b97\u6cd5\u4e2d\uff0c\u5377\u79ef\u795e\u7ecf\u7f51\u7edc<\/u> (CNN) \u5df2\u6210\u4e3a\u56fe\u50cf\u5206\u7c7b\u7684\u9996\u9009\u89e3\u51b3\u65b9\u6848\u3002\u5176\u56fe\u50cf\u8bc6\u522b\u7684\u51c6\u786e\u7387\u975e\u5e38\u9ad8\uff0c\u56e0\u800c\u5f97\u4ee5\u5e7f\u6cdb\u5e94\u7528\u4e8e\u591a\u79cd\u5e94\u7528\uff0c\u8de8\u8d8a\u4e0d\u540c\u7684\u5e73\u53f0\uff0c\u4f8b\u5982\u667a\u80fd\u624b\u673a\u3001\u5b89\u9632\u7cfb\u7edf\u548c\u6c7d\u8f66\u9a7e\u9a76\u5458\u8f85\u52a9\u7cfb\u7edf\u3002\u4f5c\u4e3a\u4e00\u79cd\u6df1\u5ea6\u795e\u7ecf\u7f51\u7edc (DNN)\uff0cCNN \u4f7f\u7528\u7684\u795e\u7ecf\u7f51\u7edc\u67b6\u6784\u7531\u4e13\u7528\u5c42\u6784\u6210\u3002\u5728\u5bf9\u6807\u6ce8\u56fe\u50cf\u8fdb\u884c\u8bad\u7ec3\u671f\u95f4\uff0c\u5b83\u4f1a\u4ece\u56fe\u50cf\u4e2d\u63d0\u53d6\u7279\u5f81\uff0c\u5e76\u4f7f\u7528\u8fd9\u4e9b\u7279\u5f81\u7ed9\u56fe\u50cf\u5206\u7c7b\uff08\u53c2\u89c1“\u5229\u7528\u73b0\u6210\u7684\u8f6f\u786c\u4ef6\u542f\u52a8\u673a\u5668\u5b66\u4e60”\uff09\u3002<\/p>\n

\n\tCNN \u5f00\u53d1\u4eba\u5458\u901a\u5e38\u5728\u9ad8\u6027\u80fd\u7cfb\u7edf\u6216\u4e91\u5e73\u53f0\u4e0a\u8fdb\u884c\u8bad\u7ec3\uff0c\u4f7f\u7528\u56fe\u5f62\u5904\u7406\u5355\u5143 (GPU<\/u>) \u52a0\u901f\u5728\u6807\u6ce8\u56fe\u50cf\u6570\u636e\u96c6\uff08\u901a\u5e38\u6570\u4ee5\u767e\u4e07\u8ba1\uff09\u4e0a\u8bad\u7ec3\u6a21\u578b\u6240\u9700\u7684\u5de8\u91cf\u77e9\u9635\u8ba1\u7b97\u3002\u8bad\u7ec3\u5b8c\u6210\u4e4b\u540e\uff0c\u8bad\u7ec3\u597d\u7684\u6a21\u578b\u7528\u5728\u63a8\u7406\u5e94\u7528\u4e2d\uff0c\u5bf9\u89c6\u9891\u6d41\u4e2d\u7684\u65b0\u56fe\u50cf\u6216\u5e27\u8fdb\u884c\u5206\u7c7b\u3002\u63a8\u7406\u90e8\u7f72\u5b8c\u6210\u540e\uff0c\u8bad\u7ec3\u597d\u7684\u6a21\u578b\u4ecd\u7136\u9700\u8981\u6267\u884c\u540c\u6837\u7684\u77e9\u9635\u8ba1\u7b97\uff0c\u4f46\u7531\u4e8e\u8f93\u5165\u91cf\u8981\u5c11\u5f88\u591a\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u5c06 CNN \u7528\u4e8e\u5728\u901a\u7528\u786c\u4ef6\u4e0a\u8fd0\u884c\u7684\u666e\u901a\u673a\u5668\u5b66\u4e60\u5e94\u7528\uff08\u53c2\u89c1“\u5229\u7528 Raspberry Pi<\/u> \u6784\u5efa\u673a\u5668\u5b66\u4e60\u5e94\u7528”\uff09\u3002<\/p>\n

\n\t\u7136\u800c\uff0c\u5bf9\u4e8e\u8bb8\u591a\u5e94\u7528\u800c\u8a00\uff0c\u901a\u7528\u5e73\u53f0\u7f3a\u4e4f\u5728 CNN \u63a8\u7406\u4e2d\u540c\u65f6\u5b9e\u73b0\u9ad8\u51c6\u786e\u7387\u548c\u9ad8\u6027\u80fd\u6240\u9700\u7684\u6027\u80fd\u3002\u4f18\u5316\u6280\u672f\u548c\u66ff\u4ee3 CNN \u67b6\u6784\uff08\u5982 MobileNet \u6216 SqueezeNet\uff09\u6709\u52a9\u4e8e\u964d\u4f4e\u5e73\u53f0\u8981\u6c42\uff0c\u4f46\u901a\u5e38\u4f1a\u727a\u7272\u51c6\u786e\u7387\u5e76\u589e\u52a0\u63a8\u7406\u5ef6\u65f6\uff0c\u800c\u8fd9\u53ef\u80fd\u4e0e\u5e94\u7528\u8981\u6c42\u76f8\u51b2\u7a81\u3002<\/p>\n

\n\t\u4e0e\u6b64\u540c\u65f6\uff0c\u5feb\u901f\u53d1\u5c55\u7684\u7b97\u6cd5\u4f7f\u5f97\u673a\u5668\u5b66\u4e60 IC \u7684\u8bbe\u8ba1\u5de5\u4f5c\u53d8\u5f97\u590d\u6742\uff0c\u56e0\u4e3a\u9700\u8981\u673a\u5668\u5b66\u4e60 IC \u65e2\u8981\u8db3\u591f\u4e13\u95e8\u5316\u4ee5\u52a0\u901f\u63a8\u7406\uff0c\u53c8\u8981\u8db3\u591f\u901a\u7528\u5316\u4ee5\u652f\u6301\u65b0\u7b97\u6cd5\u3002FPGA \u591a\u5e74\u6765\u4e00\u76f4\u626e\u6f14\u7740\u8fd9\u4e00\u7279\u5b9a\u89d2\u8272\uff0c\u63d0\u4f9b\u52a0\u901f\u5173\u952e\u7b97\u6cd5\u6240\u9700\u7684\u6027\u80fd\u548c\u7075\u6d3b\u6027\uff0c\u89e3\u51b3\u4e86\u901a\u7528\u5904\u7406\u5668\u6027\u80fd\u4e0d\u8db3\u6216\u6ca1\u6709\u4e13\u7528\u5668\u4ef6\u53ef\u7528\u7684\u95ee\u9898\u3002<\/p>\n

\n\tFPGA \u4f5c\u4e3a\u673a\u5668\u5b66\u4e60\u5e73\u53f0<\/h2>\n

\n\t\u5bf9\u4e8e\u673a\u5668\u5b66\u4e60\u800c\u8a00\uff0cGPU \u4ecd\u7136\u662f\u6807\u6746——\u8fd9\u662f\u65e9\u671f\u7684 FPGA \u6839\u672c\u65e0\u6cd5\u4f01\u53ca\u7684\u3002\u6700\u8fd1\u51fa\u73b0\u7684\u4e00\u4e9b\u5668\u4ef6\uff0c\u5982 Intel<\/u> Arria 10 GX FPGA \u548c Lattice<\/u> Semiconductor ECP5 FPGA\uff0c\u5927\u5927\u7f29\u5c0f\u4e86\u5148\u8fdb FPGA \u548c GPU \u4e4b\u95f4\u7684\u5dee\u8ddd\u3002\u5bf9\u4e8e\u67d0\u4e9b\u4f7f\u7528\u7d27\u51d1\u7684\u6574\u6570\u6570\u636e\u7c7b\u578b\u7684 DNN \u67b6\u6784\u6765\u8bf4\uff0c\u6b64\u7c7b FPGA \u7684\u6027\u80fd\/\u529f\u8017\u6bd4\u751a\u81f3\u9ad8\u4e8e\u4e3b\u6d41 GPU\u3002<\/p>\n

\n\t\u9ad8\u7ea7 FPGA \u7ec4\u5408\u4e86\u5d4c\u5165\u5f0f\u5b58\u50a8\u5668\u548c\u6570\u5b57\u4fe1\u53f7\u5904\u7406 (DSP<\/u>) \u8d44\u6e90\uff0c\u5bf9\u4e8e\u4e00\u822c\u77e9\u9635\u4e58\u6cd5 (GEMM) \u8fd0\u7b97\u80fd\u591f\u5b9e\u73b0\u5f88\u9ad8\u7684\u6027\u80fd\u3002\u5176\u5d4c\u5165\u5f0f\u5b58\u50a8\u5668\u9760\u8fd1\u8ba1\u7b97\u5f15\u64ce\uff0c\u4ece\u800c\u7f13\u89e3\u4e86 CPU<\/u> \u5b58\u50a8\u5668\u74f6\u9888\uff0c\u800c\u8fd9\u79cd\u74f6\u9888\u901a\u5e38\u4f1a\u9650\u5236\u901a\u7528\u5904\u7406\u5668\u4e0a\u673a\u5668\u5b66\u4e60\u7b97\u6cd5\u7684\u6027\u80fd\u3002\u53cd\u4e4b\uff0c\u76f8\u6bd4\u4e8e\u5178\u578b DSP \u5668\u4ef6\uff08\u56fe 1\uff09\uff0cFPGA \u4e0a\u7684\u5d4c\u5165\u5f0f DSP \u8ba1\u7b97\u5f15\u64ce\u63d0\u4f9b\u4e86\u66f4\u591a\u7684\u5e76\u884c\u4e58\u6cd5\u5668\u8d44\u6e90\u3002FPGA \u5382\u5546\u5728\u4ea4\u4ed8\u4e13\u95e8\u7528\u4e8e\u673a\u5668\u5b66\u4e60\u7684 FPGA \u5f00\u53d1\u5e73\u53f0\u65f6\u5145\u5206\u5229\u7528\u4e86\u8fd9\u4e9b\u7279\u6027\u3002<\/p>\n

\n\t\"Lattice<\/p>\n

\n\t\u56fe 1\uff1aLatti<\/u>ce Semiconductor ECP5 \u4e4b\u7c7b\u7684\u9ad8\u7ea7 FPGA \u63d0\u4f9b\u4e86\u5b9e\u73b0\u9ad8\u6027\u80fd\u63a8\u7406\u6240\u9700\u7684\u5e76\u884c\u5904\u7406\u8d44\u6e90\u548c\u5d4c\u5165\u5f0f\u5b58\u50a8\u5668\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aLattice Semiconductor\uff09<\/p>\n

\n\t\u4f8b\u5982\uff0cInte<\/u>l \u6700\u8fd1\u63a8\u51fa\u7684\u652f\u6301 FPGA \u7684 OPENVINO™ \u6269\u5c55\u4e86\u8be5\u5e73\u53f0\u5c06\u63a8\u7406\u6a21\u578b\u90e8\u7f72\u5230\u4e0d\u540c\u7c7b\u578b\u8bbe\u5907\uff08\u5305\u62ec GPU\u3001CPU \u548c FPGA\uff09\u7684\u80fd\u529b\u3002\u5728\u8be5\u5e73\u53f0\u4e0a\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4f7f\u7528 Intel \u7684\u6df1\u5ea6\u5b66\u4e60<\/u>\u63a8\u7406\u5f15\u64ce\u5de5\u4f5c\u6d41\u7a0b\uff0c\u5176\u4e2d\u6574\u5408\u4e86 Intel \u6df1\u5ea6\u5b66\u4e60\u90e8\u7f72\u5de5\u5177\u5305\u548c\u5728 Intel OPENVINO \u5de5\u5177\u5305\u4e2d\u63d0\u4f9b\u7684 Intel \u8ba1\u7b97\u673a\u89c6\u89c9\u8f6f\u4ef6\u5f00\u53d1\u5957\u4ef6 (SDK)\u3002\u5f00\u53d1\u4eba\u5458\u4f7f\u7528 SDK \u7684\u5e94\u7528\u7f16\u7a0b\u63a5\u53e3 (API) \u6784\u5efa\u6a21\u578b\uff0c\u5e76\u4e14\u53ef\u5229\u7528 Intel \u7684\u8fd0\u884c\u6a21\u578b\u4f18\u5316\u5668\u9488\u5bf9\u4e0d\u540c\u786c\u4ef6\u5e73\u53f0\u8fdb\u884c\u4f18\u5316\u3002<\/p>\n

\n\t\u6df1\u5ea6\u5b66\u4e60\u90e8\u7f72\u5de5\u5177\u5305\u65e8\u5728\u4e0e Intel DK-DEV-10AX115S-A Arria 10 GX FPGA \u5f00\u53d1\u5957\u4ef6\u914d\u5408\u4f7f\u7528\uff0c\u8ba9\u5f00\u53d1\u4eba\u5458\u80fd\u4ece\u9886\u5148\u7684 ML \u6846\u67b6\uff08\u5305\u62ec Caffe \u548c TensorFlow<\/u>\uff09\u5bfc\u5165\u8bad\u7ec3\u597d\u7684\u6a21\u578b\uff08\u56fe 2\uff09\u3002\u5728\u8bf8\u5982 Arria 10 GX FPGA \u5f00\u53d1\u5957\u4ef6\u4e4b\u7c7b\u76ee\u6807\u5e73\u53f0\u6216\u4f7f\u7528 Arria 10 GX FPGA \u5668\u4ef6\u7684\u5b9a\u5236\u8bbe\u8ba1\u4e0a\uff0c\u5de5\u5177\u5305\u4e2d\u7684\u6a21\u578b\u4f18\u5316\u5668\u548c\u63a8\u7406\u5f15\u64ce\u5206\u522b\u5904\u7406\u6a21\u578b\u8f6c\u6362\u548c\u90e8\u7f72\u3002<\/p>\n

\n\t\"\u652f\u6301<\/p>\n

\n\t\u56fe 2\uff1a\u652f\u6301 FPGA \u7684 Intel OPENVINO \u5de5\u5177\u5305\u63d0\u4f9b\u4e86\u4e00\u5957\u5fc5\u9700\u7684\u5b8c\u6574\u5de5\u5177\u94fe\uff0c\u53ef\u5c06\u5728 Caffe\u3001TensorFlow \u548c\u5176\u4ed6\u6846\u67b6\u4e0a\u8bad\u7ec3\u7684\u6a21\u578b\u90e8\u7f72\u5230 Arria 10 GX FPGA \u5f00\u53d1\u5957\u4ef6\u6216\u56f4\u7ed5 Arria 10 GX FPGA \u6784\u5efa\u7684\u5b9a\u5236\u8bbe\u8ba1\u4e0a\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aIntel\uff09<\/p>\n

\n\t\u4e3a\u4e86\u8fc1\u79fb\u9884\u8bad\u7ec3\u6a21\u578b\uff0c\u5f00\u53d1\u4eba\u5458\u4f7f\u7528\u57fa\u4e8e Python<\/u> \u7684\u6a21\u578b\u4f18\u5316\u5668\u751f\u6210\u4e86\u4e00\u4e2a\u4e2d\u95f4\u8868\u793a (IR)\uff0c\u8be5\u8868\u793a\u5305\u542b\u5728\u4e00\u4e2a\u63d0\u4f9b\u7f51\u7edc\u62d3\u6251\u7684 xml \u6587\u4ef6\u548c\u4e00\u4e2a\u4ee5\u4e8c\u8fdb\u5236\u503c\u63d0\u4f9b\u6a21\u578b\u53c2\u6570\u7684 bin \u6587\u4ef6\u4e2d\u3002\u9664\u4e86\u751f\u6210 IR \u4e4b\u5916\uff0c\u6a21\u578b\u4f18\u5316\u5668\u8fd8\u4f1a\u6267\u884c\u4e00\u9879\u5173\u952e\u529f\u80fd——\u79fb\u9664\u6a21\u578b\u4e2d\u7528\u4e8e\u8bad\u7ec3\u4f46\u5bf9\u63a8\u7406\u6beb\u65e0\u4f5c\u7528\u7684\u5c42\u3002\u6b64\u5916\uff0c\u8be5\u5de5\u5177\u4f1a\u5728\u53ef\u80fd\u7684\u60c5\u51b5\u4e0b\u5c06\u6bcf\u4e2a\u63d0\u4f9b\u72ec\u7acb\u6570\u5b66\u8fd0\u7b97\u7684\u5c42\u5408\u5e76\u5230\u4e00\u4e2a\u7ec4\u5408\u5c42\u4e2d\u3002<\/p>\n

\n\t\u901a\u8fc7\u8fd9\u79cd\u7f51\u7edc\u4fee\u526a\u548c\u5408\u5e76\uff0c\u6a21\u578b\u53d8\u5f97\u66f4\u7d27\u51d1\uff0c\u8fdb\u800c\u52a0\u5feb\u63a8\u7406\u65f6\u95f4\u5e76\u51cf\u5c11\u5bf9\u76ee\u6807\u5e73\u53f0\u7684\u5b58\u50a8\u5668\u9700\u6c42\u3002<\/p>\n

\n\tIntel \u63a8\u7406\u5f15\u64ce\u662f\u4e00\u4e2a C++<\/u> \u5e93\uff0c\u5176\u4e2d\u5305\u542b\u4e00\u7ec4 C++ \u7c7b\u3002\u8fd9\u4e9b\u7c7b\u5bf9\u4e8e\u53d7\u652f\u6301\u7684\u76ee\u6807\u786c\u4ef6\u5e73\u53f0\u6765\u8bf4\u662f\u901a\u7528\u7684\uff0c\u56e0\u6b64\u53ef\u4ee5\u5728\u5404\u4e2a\u5e73\u53f0\u4e0a\u5b9e\u73b0\u63a8\u7406\u3002\u5bf9\u4e8e\u63a8\u7406\u5e94\u7528\u800c\u8a00\uff0c\u5f00\u53d1\u4eba\u5458\u4f7f\u7528\u50cf CNNNetReader \u8fd9\u6837\u7684\u7c7b\u6765\u8bfb\u53d6 xml \u6587\u4ef6 (ReadNetwork) \u4e2d\u5305\u542b\u7684 CNN \u62d3\u6251\u4ee5\u53ca bin \u6587\u4ef6 (ReadWeights) \u4e2d\u5305\u542b\u7684\u6a21\u578b\u53c2\u6570\u3002\u6a21\u578b\u52a0\u8f7d\u5b8c\u6210\u540e\uff0c\u8c03\u7528\u7c7b\u65b9\u6cd5 Infer() \u6267\u884c\u963b\u585e\u63a8\u7406\uff0c\u540c\u65f6\u8c03\u7528\u7c7b\u65b9\u6cd5 StartAsync() \u6267\u884c\u5f02\u6b65\u63a8\u7406\uff0c\u5f53\u63a8\u7406\u5b8c\u6210\u65f6\u4f7f\u7528\u7b49\u5f85\u6216\u5b8c\u6210\u4f8b\u7a0b\u5904\u7406\u7ed3\u679c\u3002<\/p>\n

\n\tIntel \u5728 OPENVINO \u73af\u5883\u63d0\u4f9b\u7684\u591a\u4e2a\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u4e2d\u6f14\u793a\u4e86\u5b8c\u6574\u7684\u5de5\u4f5c\u6d41\u7a0b\u548c\u8be6\u7ec6\u7684\u63a8\u7406\u5f15\u64ce API \u8c03\u7528\u3002\u4f8b\u5982\uff0c\u5b89\u5168\u5c4f\u969c\u6444\u50cf\u673a\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u5c55\u793a\u4e86\u4f7f\u7528\u63a8\u7406\u6a21\u578b\u6d41\u6c34\u7ebf\uff0c\u4ee5\u9996\u5148\u786e\u5b9a\u8f66\u8f86\u8fb9\u754c\u6846\uff08\u56fe 3\uff09\u3002\u6d41\u6c34\u7ebf\u4e2d\u7684\u4e0b\u4e00\u4e2a\u6a21\u578b\u68c0\u67e5\u4e86\u8fb9\u754c\u6846\u4e2d\u7684\u5185\u5bb9\uff0c\u8bc6\u522b\u8f66\u8f86\u7c7b\u522b\u3001\u989c\u8272\u548c\u8f66\u724c\u4f4d\u7f6e\u7b49\u8f66\u8f86\u5c5e\u6027\u3002<\/p>\n

\n\t\"Intel<\/p>\n

\n\t\u56fe 3\uff1aIntel \u5b89\u5168\u5c4f\u969c\u6444\u50cf\u673a\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u6f14\u793a\u4e86\u4f7f\u7528\u63a8\u7406\u6d41\u6c34\u7ebf\uff0c\u5148\u8bc6\u522b\u8f66\u8f86\uff08\u7eff\u8272\u8fb9\u754c\u6846\uff09\uff0c\u518d\u8bc6\u522b\u989c\u8272\u3001\u7c7b\u578b\u548c\u8f66\u724c\u4f4d\u7f6e\uff08\u7ea2\u8272\u6846\uff09\u7b49\u8f66\u8f86\u5c5e\u6027\uff0c\u6700\u540e\u8bc6\u522b\u8f66\u724c\u5b57\u7b26\uff08\u7ea2\u8272\u6587\u672c\uff09\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aIntel Corp.\uff09<\/p>\n

\n\t\u6d41\u6c34\u7ebf\u4e2d\u7684\u6700\u540e\u4e00\u4e2a\u6a21\u578b\u4f7f\u7528\u8fd9\u4e9b\u8f66\u8f86\u5c5e\u6027\u4ece\u8f66\u724c\u4e2d\u63d0\u53d6\u5b57\u7b26\u3002\u4e3a\u4e86\u4f7f\u7528\u8be5\u6a21\u578b\u8fdb\u884c\u63a8\u7406\uff0c\u793a\u4f8b\u4ee3\u7801\u663e\u793a\u4e86\u5229\u7528\u63a8\u7406\u6a21\u578b C++ \u5e93\u521b\u5efa\u5bf9\u8c61 (LPR)\uff0c\u800c\u8be5\u5bf9\u8c61\u5219\u662f\u540d\u4e3a LPRDetection \u7684\u7ed3\u6784\u7684\u4e00\u4e2a\u5b9e\u4f8b\u3002\u6b64\u7ed3\u6784\u4f7f\u7528\u63a8\u7406\u5f15\u64ce API \u7c7b\u5bf9\u8c61\u6765\u8bfb\u53d6 (CNNNetReader) \u5e76\u9a8c\u8bc1\u6a21\u578b\u8f93\u5165\u548c\u8f93\u51fa\uff08\u5217\u8868 1\uff09\u3002<\/p>\n

\r\n\u526f\u672c    CNNNetwork read() override {\r\n        std::cout << "[ INFO ] Loadi<\/u>ng network files for Licence Plate Recognition (LPR)" << std::endl;\r\n        CNNNetReader netReader;\r\n        \/** Read network model **\/\r\n        netReader.ReadNetwork(FLAGS_m_lpr);\r\n        std::cout << "[ INFO ] Batch size is forced to  1 for LPR Network" << std::endl;\r\n        netReader.getNetwork().setBatchSize(1);\r\n        \/** Extract model name and load it's weights **\/\r\n        std::string binFileName = fileNameNoExt(FLAGS_m_lpr) + ".bin";\r\n        netReader.ReadWeights(binFileName);\r\n \r\n        \/** LPR network should have 2 inputs (and second is just a stub) and one output **\/\r\n        \/\/ ---------------------------Check inputs\r\n        std::cout << "[ INFO ] Checking LPR Network inputs" << std::endl;\r\n        InputsDataMap inputInfo(netReader.getNetwork().getInputsInfo());\r\n        if (inputInfo.size() != 2) {\r\n            throw std::logic_error("LPR should have 2 inputs");\r\n        }\r\n        InputInfo::Ptr& inputInfoFirs<\/u>t = inputInfo.begin()->second;\r\n        inputInfoFirst->setInputPrecision(Precision::U8);\r\n        inputInfoFirst->getInputData()->setLayout(Layout::NCHW);\r\n        inputImageName = inputInfo.begin()->first;\r\n        auto sequenceInput = (++inputInfo.begin());\r\n        inputSeqName = sequenceInput->first;\r\n        if (sequenceInput->second->getTensorDesc().getDims()[0] != maxSequenceSizePerPlate) {\r\n            throw std::logic_error("LPR post-processing assumes certain maximum sequences");\r\n        }\r\n \r\n        \/\/ ---------------------------Check outputs\r\n        std::cout << "[ INFO ] Checking LPR Network outputs" << std::endl;\r\n        OutputsDataMap outputInfo(netReader.getNetwork().getOutputsInfo());\r\n        if (outputInfo.size() != 1) {\r\n            throw std::logic_error("LPR should have 1 output");\r\n        }\r\n        outputName = outputInfo.begin()->first;\r\n        std::cout << "[ INFO ] Loading LPR model to the "<< FLAGS_d_lpr << " plugin" << std::endl;\r\n \r\n        _enabled = true;\r\n        return netReader.getNetwork();\r\n    }<\/pre>\n
\n\t\u5217\u8868 1\uff1a\u6b64\u4ee3\u7801\u7247\u6bb5\u6765\u81ea Intel OPENVINO \u5de5\u5177\u5305\u4e2d\u7684\u5b89\u5168\u5c4f\u969c\u6444\u50cf\u673a\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\uff0c\u6f14\u793a\u4e86\u4f7f\u7528 Intel \u63a8\u7406\u5f15\u64ce C++ \u5e93 API \u5c06\u6a21\u578b\u53ca\u5176\u53c2\u6570\u8bfb\u5165\u63a8\u7406\u5f15\u64ce\u7684\u8bbe\u8ba1\u6a21\u5f0f\u3002\uff08\u4ee3\u7801\u6765\u6e90\uff1aIntel\uff09<\/p>\n
\n\t\u4e3a\u4e86\u6267\u884c\u63a8\u7406\uff0c\u8be5\u4ee3\u7801\u52a0\u8f7d\u6570\u636e\u5e76\u8c03\u7528 submitRequest \u65b9\u6cd5\uff0c\u8be5\u65b9\u6cd5\u542f\u52a8\u63a8\u7406\u5468\u671f\u5e76\u7b49\u5f85\u7ed3\u679c\uff0c\u7136\u540e\u663e\u793a\u8bc6\u522b\u7684\u8f66\u724c\u5b57\u7b26\uff08\u5217\u8868 2\uff09\u3002<\/p>\n
\r\n\u526f\u672c     if (LPR.enabled()) {  \/\/ licence plate\r\n         \/\/ expanding a bounding box a bit, better for the license plate recognition\r\n         result.location.x -= 5;\r\n         result.location.y -= 5;\r\n         result.location.widt<\/u>h += 10;\r\n         result.location.height += 10;\r\n         auto clippedRect = result.location & cv::Rect(0, 0, width, height);\r\n         cv::Mat Plate = fram<\/u>e(clippedRect);\r\n         \/\/ ----------------------------Run License Plate Recognition \r\n         LPR.enqueue(Plate);\r\n         t0 = std::chrono::high_resolution_clock::now();\r\n         LPR.submitRequest();\r\n         LPR.wait();\r\n         t1 = std::chrono::high_resolution_clock::now();\r\n         LPRNetworktime += std::chrono::duration_cast(t1 - t0);\r\n         LPRInferred++;\r\n         \/\/ ----------------------------Process outputs\r\n         cv::putText(frame,\r\n                     LPR.GetLicencePlateText(),\r\n                     cv::Point2f(result.location.x, result.location.y + result.location.height + 15),\r\n                     cv::FONT_HERSHEY_COMPLEX_SMALL,\r\n                     0.8,\r\n                     cv::Scalar(0, 0, 255));\r\n         if (FLAGS_r) {\r\n             std::cout << "License Plate Recognition results:" << LPR.GetLicencePlateText() << std::endl;\r\n         }\r\n     }\r\n     cv::rectangle(frame, result.location, cv::Scalar(0, 0, 255), 2);\r\n }<\/ms><\/pre>\n
\n\t\u5217\u8868 2\uff1a\u6b64\u4ee3\u7801\u7247\u6bb5\u6765\u81ea Intel OPENVINO \u5de5\u5177\u5305\u4e2d\u7684\u5b89\u5168\u5c4f\u969c\u6444\u50cf\u673a\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\uff0c\u5c55\u793a\u4e86\u52a0\u8f7d\u6a21\u578b\u3001\u6267\u884c\u63a8\u7406\u548c\u751f\u6210\u7ed3\u679c\u7684\u8bbe\u8ba1\u6a21\u5f0f\u3002\uff08\u4ee3\u7801\u6765\u6e90\uff1aIntel\uff09<\/p>\n
\n\t\u96c6\u6210\u5f0f\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e73\u53f0<\/h2>\n
\n\tIntel \u7684 OPENVINO \u65b9\u6cd5\u5f3a\u8c03\u5e73\u53f0\u91cd\u5b9a\u5411\uff0c\u800c Lattice \u7684 SensAI \u5e73\u53f0\u5b8c\u5168\u805a\u7126\u4e8e FPGA \u63a8\u7406\u3002SensAI \u5e73\u53f0\u7684\u7279\u6027\u4e4b\u4e00\u662f\u4e3a DNN \u67b6\u6784\uff08\u5305\u62ec CNN \u548c\u4e00\u4e2a\u79f0\u4e3a\u4e8c\u503c\u5316\u795e\u7ecf\u7f51\u7edc (BNN) \u7684\u7d27\u51d1\u67b6\u6784\uff09\u63d0\u4f9b FPGA IP\u3002\u9488\u5bf9\u5d4c\u5165\u5f0f\u89c6\u89c9\uff0cSensAI CNN IP \u4e3a\u5b8c\u6574\u7684\u63a8\u7406\u5f15\u64ce\u63d0\u4f9b\u6846\u67b6\uff0c\u5c06\u63a7\u5236\u5b50\u7cfb\u7edf\u3001\u5b58\u50a8\u5668\u3001\u8f93\u5165\u548c\u8f93\u51fa\u7684\u63a5\u53e3\u4e0e\u5b9e\u73b0\u4e0d\u540c\u7c7b\u578b\u6a21\u578b\u5c42\uff08\u5305\u62ec\u5377\u79ef\u3001BatchNorm \u5f52\u4e00\u5316\u3001ReLu \u6fc0\u6d3b\u3001\u6c60\u5316\u548c\u5176\u4ed6\uff09\u7684\u8d44\u6e90\u7ed3\u5408\u5728\u4e00\u8d77\uff08\u56fe 4\uff09\u3002<\/p>\n
\n\t\"Lattice<\/p>\n
\n\t\u56fe 4\uff1aLattice Semiconductor CNN IP \u5b9e\u73b0\u4e86\u4e00\u4e2a\u5b8c\u6574\u7684\u63a8\u7406\u7cfb\u7edf\u6846\u67b6\uff0c\u5c06\u4e13\u7528\u5f15\u64ce\u548c\u7528\u4e8e\u63a7\u5236\u3001\u5b58\u50a8\u5668\u3001\u8f93\u5165\u3001\u8f93\u51fa\u7684\u63a5\u53e3\u7ed3\u5408\u5728\u4e00\u8d77\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aLattice Semiconductor\uff09<\/p>\n
\n\t\u4e3a\u4e86\u5b9e\u73b0 CNN \u6a21\u578b\uff0c\u5f00\u53d1\u4eba\u5458\u9996\u5148\u8981\u5728\u9488\u5bf9 ECP5 FPGA \u7684 Lattice Diamond \u8bbe\u8ba1\u73af\u5883\u4e2d\u6216\u9488\u5bf9\u5176\u4ed6 Lattice FPGA \u7cfb\u5217\u7684 Radiant \u8bbe\u8ba1\u73af\u5883\u4e2d\uff0c\u5229\u7528 Lattice Clarity \u914d\u7f6e\u5de5\u5177\u914d\u7f6e CNN\u3002\u8fd9\u91cc\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u6307\u5b9a\u6a21\u578b\u7c7b\u578b\uff08CNN \u6216 BNN\uff09\u3001\u5377\u79ef\u5f15\u64ce\u6570\uff08\u6700\u591a 8 \u4e2a\uff09\u53ca\u6bcf\u5c42\u7684\u5185\u90e8\u5b58\u50a8\u5927\u5c0f\uff08\u6700\u591a 16 Kb\uff09\u6216\u4e8c\u8fdb\u5236\u5927\u5bf9\u8c61 (blob)\u3002\u914d\u7f6e CNN \u4e4b\u540e\uff0c\u5f00\u53d1\u4eba\u5458\u4f7f\u7528\u8bbe\u8ba1\u73af\u5883\u751f\u6210\u6838\u5fc3\uff0c\u4f5c\u4e3a FPGA \u6bd4\u7279\u6d41\u3002<\/p>\n
\n\t\u5f00\u53d1\u4eba\u5458\u5355\u72ec\u5c06\u901a\u8fc7 Caffe \u6216 TensorFlow \u5f00\u53d1\u5e76\u8bad\u7ec3\u597d\u7684\u6a21\u578b\u5bfc\u5165 SensAI \u5e73\u53f0\u3002\u8fd9\u91cc\uff0cLattice \u795e\u7ecf\u7f51\u7edc\u7f16\u8bd1\u5668\u5c06\u8bad\u7ec3\u597d\u7684 Caffe \u6216 TensorFlow \u6a21\u578b\u8f6c\u6362\u4e3a\u4e00\u7ec4\u5305\u542b\u795e\u7ecf\u7f51\u7edc\u6a21\u578b\u53c2\u6570\u548c\u6267\u884c\u547d\u4ee4\u5e8f\u5217\u7684\u6587\u4ef6\u3002SensAI \u5e73\u53f0\u5c06\u6765\u81ea\u8bbe\u8ba1\u73af\u5883\u548c\u7f16\u8bd1\u5668\u7684\u5355\u72ec\u8f93\u51fa\u4e00\u8d77\u5e76\u5165 FPGA\uff0c\u4ee5\u63d0\u4f9b\u6700\u7ec8\u7684\u63a8\u7406\u6a21\u578b\uff08\u56fe 5\uff09\u3002<\/p>\n
\n\t\"Lattice<\/p>\n
\n\t\u56fe 5\uff1aLattice Semiconductor SensAI \u5e73\u53f0\u5c06\u5176 CNN \u548c BNN IP \u4e0e\u5176\u795e\u7ecf\u7f51\u7edc\u7f16\u8bd1\u5668\u7ed3\u5408\u5728\u4e00\u8d77\uff0c\u4f7f\u5f00\u53d1\u4eba\u5458\u80fd\u591f\u8f6c\u6362 Caffe \u6216 TensorFlow \u6a21\u578b\uff0c\u4ee5\u5728 Lattice FPGA \u4e0a\u4f5c\u4e3a\u63a8\u7406\u5f15\u64ce\u6765\u8fd0\u884c\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aLattice Semiconductor\uff09<\/p>\n
\n\t\u9488\u5bf9\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94\u7528\uff0cLattice LF-EVDK1-EVN \u5d4c\u5165\u5f0f\u89c6\u89c9\u5f00\u53d1\u5957\u4ef6 (EVDK) \u4e3a\u8fd0\u884c CNN \u6a21\u578b\u63a8\u7406\u63d0\u4f9b\u4e86\u7406\u60f3\u7684\u76ee\u6807\u5e73\u53f0\u3002EVDK \u63d0\u4f9b\u4e86\u4e00\u4e2a\u5b8c\u6574\u7684 80 x 80 mm \u4e09\u677f\u5806\u53e0\u5f0f\u89c6\u9891\u5e73\u53f0\uff0c\u5305\u62ec Lattice CrossLink \u89c6\u9891\u8f93\u5165\u677f\u3001\u5e26 ECP5 FPGA \u7684\u5904\u7406\u5668\u677f\u548c HDMI<\/u> \u8f93\u51fa\u677f\u3002\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u5c06 EVDK \u7528\u4f5c Lattice \u63d0\u4f9b\u7684\u591a\u4e2a\u793a\u4f8b CNN \u5e94\u7528\u7684\u76ee\u6807\u5e73\u53f0\u3002\u4f8b\u5982\uff0cLattice \u901f\u5ea6\u6807\u5fd7\u68c0\u6d4b\u53c2\u8003\u8bbe\u8ba1\u8fd0\u7528 EVDK \u6765\u5c55\u793a SensAI CNN IP \u5728\u5178\u578b\u6c7d\u8f66\u5e94\u7528\u4e2d\u7684\u5e94\u7528\uff08\u56fe 6\uff09\u3002<\/p>\n
\n\t\"Lattice<\/p>\n
\n\t\u56fe 6\uff1aLattice Semiconductor \u901f\u5ea6\u6807\u5fd7\u68c0\u6d4b\u53c2\u8003\u8bbe\u8ba1\u5229\u7528 SensAI \u5e73\u53f0\u548c Lattice LF_EVDK1-EVN \u5d4c\u5165\u5f0f\u89c6\u89c9\u5f00\u53d1\u5957\u4ef6\u63d0\u4f9b\u4e00\u4e2a\u5b8c\u6574\u7684\u63a8\u7406\u5e94\u7528\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u5bf9\u5176\u7acb\u5373\u64cd\u4f5c\u6216\u8be6\u7ec6\u63a2\u7d22\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aLattice Semiconductor\uff09<\/p>\n
\n\t\u6b64\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u7684\u9879\u76ee\u6587\u4ef6\u5305\u62ec\u5168\u5957\u6587\u4ef6\uff0c\u4ece Caffe caffemodel \u548c TensorFlow pb \u683c\u5f0f\u7684\u6a21\u578b\u5f00\u59cb\u3002\u56e0\u6b64\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u63a2\u7d22\u8fd9\u4e9b\u6a21\u578b\u7684\u7ec6\u8282\u3002\u4f8b\u5982\uff0c\u4f7f\u7528 TensorFlow import_pb_to_tensorboard.py \u5b9e\u7528\u7a0b\u5e8f\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u5bfc\u5165 Lattice \u63d0\u4f9b\u7684 pb \u6a21\u578b\uff0c\u4ee5\u67e5\u770b\u6b64\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u4e2d\u4f7f\u7528\u7684 CNN \u7684\u7ec6\u8282\uff08\u56fe 7\uff09\u3002\u672c\u4f8b\u4e2d\uff0c\u6240\u63d0\u4f9b\u7684\u6a21\u578b\u662f\u7531\u56db\u4e2a“Fire”\u6a21\u5757\u7ec4\u6210\u7684\u5e8f\u5217\uff0c\u6bcf\u4e2a\u6a21\u5757\u5305\u62ec\uff1a<\/p>\n
    \n
  • \n
    \n\t\t\tConv2D \u5c42\uff0c\u6267\u884c 3 x 3 \u5377\u79ef\u4ee5\u4ece\u8f93\u5165\u6d41\u4e2d\u63d0\u53d6\u7279\u5f81<\/p>\n<\/li>\n
  • \n
    \n\t\t\t\u6fc0\u6d3b\u5c42\uff0c\u6267\u884c BatchNorm \u5f52\u4e00\u5316\uff0c\u7136\u540e\u6267\u884c\u4fee\u6b63\u7ebf\u6027\u5355\u5143 (ReLU) \u6fc0\u6d3b<\/p>\n<\/li>\n
  • \n
    \n\t\t\tMaxPool \u6c60\u5316\u5c42\uff0c\u7528\u4e8e\u5bf9\u524d\u4e00\u5c42\u7684\u8f93\u51fa\u8fdb\u884c\u91c7\u6837<\/p>\n<\/li>\n<\/ul>\n
    \n\t\"Lattice<\/p>\n
    \n\t\u56fe 7\uff1aLattice \u901f\u5ea6\u6807\u5fd7\u68c0\u6d4b\u793a\u4f8b\u5e94\u7528\u7a0b\u5e8f\u5305\u62ec TensorFlow pb \u6a21\u578b\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u5c06\u5176\u5bfc\u5165 TensorBoard \u8fdb\u884c\u8be6\u7ec6\u68c0\u67e5\u3002\u6ce8\u610f\uff1a\u6570\u636e\u5411\u4e0a\u6d41\u8fc7\u6b64\u56fe\u4e2d\u7684\u5404\u5c42\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aDigi-Key<\/u> Electronics\uff09<\/p>\n
    \n\t\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u4f7f\u7528 SensAI \u5e73\u53f0\u751f\u6210\u6a21\u578b\u6587\u4ef6\uff0c\u5b8c\u6210\u524d\u9762\u63cf\u8ff0\u7684\u6a21\u578b\u6d41\u7a0b\u3002\u6216\u8005\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u4f7f\u7528\u6240\u63d0\u4f9b\u7684\u6587\u4ef6\u76f4\u63a5\u8df3\u8f6c\u5230\u90e8\u7f72\u9636\u6bb5\u3002\u4efb\u4e00\u60c5\u51b5\u4e0b\uff0c\u6587\u4ef6\u90fd\u662f\u901a\u8fc7\u63a5\u6709\u9002\u914d\u5668\u7684 microSD \u5361\u52a0\u8f7d\u5230 EVDK \u4e2d\u3002<\/p>\n
    \n\t\u5728\u64cd\u4f5c\u4e2d\uff0cEVDK \u4e0a\u7684\u6444\u50cf\u673a\u5411 ECP5 FPGA \u63d0\u4f9b\u89c6\u9891\u6d41\uff0c\u5176\u4e2d\u914d\u7f6e\u7684 CNN \u52a0\u901f\u5668 IP \u6267\u884c\u547d\u4ee4\u5e8f\u5217\u4ee5\u6267\u884c\u63a8\u7406\u3002\u540c\u4efb\u4f55\u63a8\u7406\u5f15\u64ce\u4e00\u6837\uff0c\u6bcf\u4e2a\u8f93\u51fa\u901a\u9053\u90fd\u4f1a\u4ea7\u751f\u4e00\u4e2a\u7ed3\u679c\uff0c\u6307\u51fa\u4e0e\u8be5\u8f93\u51fa\u901a\u9053\u76f8\u5173\u8054\u7684\u6807\u7b7e\u5373\u4e3a\u8f93\u5165\u56fe\u50cf\u7684\u6821\u6b63\u6807\u7b7e\u7684\u6982\u7387\u3002\u672c\u4f8b\u4e2d\uff0c\u6a21\u578b\u662f\u7528\u6bcf\u5c0f\u65f6 25\u300130\u300135\u300140\u300145\u300150\u300155\u300160 \u548c 65 \u82f1\u91cc\u7684\u9650\u901f\u6807\u5fd7\u7684\u6807\u6ce8\u56fe\u50cf\u8fdb\u884c\u8bad\u7ec3\u7684\u3002\u56e0\u6b64\uff0c\u5f53\u6a21\u578b\u5728\u5176\u8f93\u5165\u5b57\u6bb5\u4e2d\u7684\u4efb\u4f55\u4f4d\u7f6e\u68c0\u6d4b\u5230\u9650\u901f\u6807\u5fd7\u65f6\uff0c\u5b83\u4f1a\u663e\u793a\u68c0\u6d4b\u5230\u7684\u6807\u5fd7\u5bf9\u5e94\u4e8e\u6bcf\u5c0f\u65f6 25\u300130\u300135\u300140\u300145\u300150\u300155\u300160 \u6216 65 \u82f1\u91cc\u9650\u901f\u7684\u6982\u7387\uff08\u56fe 8\uff09\u3002<\/p>\n
    \n\t\"Lattice<\/p>\n
    \n\t\u56fe 8\uff1aLattice \u901f\u5ea6\u6807\u5fd7\u68c0\u6d4b\u6f14\u793a\u8fd0\u884c\u5728 Lattice EVDK \u4e0a\uff0c\u5bf9\u89c6\u9891\u8f93\u5165\u6d41\u6267\u884c\u63a8\u7406\uff0c\u751f\u6210\u8f93\u51fa\u503c\uff0c\u6307\u793a\u6355\u83b7\u5230\u7684\u56fe\u50cf\u5bf9\u5e94\u4e8e\u4e0e\u8be5\u7279\u5b9a\u8f93\u51fa\u76f8\u5173\u8054\u7684\u6807\u7b7e\u7684\u53ef\u80fd\u6027\u3002\u672c\u4f8b\u4e2d\uff0c\u5b83\u663e\u793a\u9650\u901f\u6807\u5fd7\u6700\u6709\u53ef\u80fd\u662f 25 mph\u3002\uff08\u56fe\u7247\u6765\u6e90\uff1aLattice Semiconductor\uff09<\/p>\n
    \n\t\u603b\u7ed3<\/h2>\n
    \n\t\u4e3a\u5728\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94\u7528\u4e2d\u8fd0\u7528\u673a\u5668\u5b66\u4e60\uff0c\u5f00\u53d1\u4eba\u5458\u4f7f\u7528\u53ef\u7528\u786c\u4ef6\u5e73\u53f0\u5b9e\u73b0\u6240\u9700\u6027\u80fd\u6c34\u5e73\u7684\u80fd\u529b\u53d7\u5230\u4e86\u9650\u5236\u3002\u7136\u800c\uff0c\u9ad8\u6027\u80fd FPGA \u7684\u51fa\u73b0\u4f7f\u5f97\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u6784\u5efa\u6027\u80fd\u63a5\u8fd1 GPU \u7684\u63a8\u7406\u5f15\u64ce\u3002\u91c7\u7528\u4e13\u4e3a\u5d4c\u5165\u5f0f\u89c6\u89c9\u8bbe\u8ba1\u7684\u673a\u5668\u5b66\u4e60 FPGA \u5e73\u53f0\uff0c\u5f00\u53d1\u4eba\u5458\u53ef\u4ee5\u4e13\u6ce8\u4e8e\u7279\u5b9a\u9700\u6c42\uff0c\u4f7f\u7528\u6807\u51c6\u673a\u5668\u5b66\u4e60\u6846\u67b6\u8bad\u7ec3\u6a21\u578b\uff0c\u5e76\u4f9d\u9760 FPGA \u5e73\u53f0\u5b9e\u73b0\u9ad8\u6027\u80fd\u63a8\u7406\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"
    \u968f\u7740\u6444\u50cf\u5934\u548c\u5176\u4ed6\u8bbe\u5907\u4ea7\u751f\u7684\u6570\u636e\u5728\u5feb\u901f\u589e\u957f\uff0c\u4fc3\u4f7f\u4eba\u4eec\u8fd0\u7528 \u673a\u5668\u5b66\u4e60 \u4ece\u6c7d\u8f66\u3001\u5b89\u9632\u548c\u5176\u4ed6\u5e94\u7528\u4ea7\u751f\u7684\u5f71\u50cf\u4e2d\u63d0\u53d6\u66f4\u591a\u6709\u7528\u7684\u4fe1\u606f\u3002\u4e13\u7528\u5668\u4ef6\u6709\u671b\u5728\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94\u7528\u4e2d\u5b9e\u73b0\u9ad8\u6027\u80fd\u673a\u5668<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[21],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/1003"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1003"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/1003\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1003"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1003"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1003"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}